Non-volatile memory has become increasingly important for mass storage media, cards and code flash products. Non-volatile memory cells that are electrically programmable and erasable can be realized as charge-trapping memory cells, which comprise a memory layer sequence of dielectric materials with a memory layer confined between confinement layers of dielectric material, the latter having a larger energy band gap than the dielectric material of the memory layer.
The memory layer sequence is arranged between a channel region within a semiconductor body and a gate electrode of a transistor, the gate electrode being provided to control the channel by means of an applied electric voltage. Examples of charge-trapping memory cells are the SONOS memory cells, in which each confinement layer is an oxide and the memory layer is a nitride of the semiconductor material, commonly silicon (see e.g., U.S. Pat. No. 5,768,192 and U.S. Pat. No. 6,011,725, which are incorporated herein by reference).
Applying a huge enough positive voltage to the control gate of a SONOS device will generate an electrical field condition for tunnelling of electrons from an inversion channel below the gate through the confinement layer. These electrons can then be trapped in the charge trapping layer. The trapped charge carriers change the threshold voltage of the cell transistor structure. Different programming states can be read by applying the appropriate reading voltages.
According to a planar memory cell concept as shown, e.g., in Eitan, et al., “Can NROM, a 2-bit, trapping Storage NVM cell, give a real challenge to floating gate cells?”, Proc. Solid State Devices and Materials, pp. 1-3, Tokyo 1999, which is incorporated herein by reference, charge-trapping memory devices can be provided with, e.g., buried bit lines, which electrically connect the source/drain regions of the memory cells. A memory layer sequence, typically an oxide-nitride-oxide layer sequence, is located above the channel regions between corresponding source/drain regions. Above the buried bit lines, a thick oxide is formed as an electrically insulating region, especially to separate the gate electrode sufficiently from the buried bit lines. The memory layer sequence is confined to the channel region and overlaps the source/drain regions only slightly.
This fundamentally new concept called “NROM” provided by Eitan, et al. has the following important features:
(a) the programming of memory cells by means of hot channel electrons is combined with a delete operation by means of hot holes;
(b) a duplicated storage location per memory cell, i.e., on both junction sides of a transistor channel region; and
(c) a reverse read operation, which allows a separate detection of the storage content on both sides of the transistor; the term “reverse” refers to the direction of the voltage drop with respect to the source and drain regions and indicates that this direction is reverse to that applied during a programming operation.
Recently, a vertical memory cell design has been developed (Willer, J., et al. in “UMEM: a U-shape Non-Volatile-Memory Cell”, Proc. IEEE NVSMW, Monterey, pp. 42-43, 2003), which is incorporated herein by reference. According to this design, the word line is buried in the substrate with, e.g., 60 nm deep trenches. Advantageously, the channel length is folded around the bottom of the word line trenches resulting in an effective channel length of, e.g., 100 . . . 150 nm. Diffusion regions are arranged adjacent to the trenches connecting neighboring memory cells, which are arranged perpendicular to the word line direction.
In this design the ONO-layer sequence is deposited on the trench sidewalls. Accordingly, the storage region within the ONO-layer sequence, or more precisely within the memory layer typically provided by a nitride layer, is adjacent to the diffusion regions in a top region of the two opposite sidewalls of the trench.
With decreasing cell sizes, trenches forming the word lines and thus the regions wherein hot charge carriers such as electrons are generated move closer with respect to each other. The mean travel distance of hot charge carriers within the substrate may amount to 70 nm. Consequently, with trench distances approaching the 100 nm limit, the probability of trapping charge carriers generated during programming of a neighboring memory cell in the memory layer of a currently passive cell exponentially increases with decreasing cell sizes. The problem is schematically depicted in FIG. 1. Erroneous bit storage may result in those memory cells, when the number of charge carriers trapped accumulates.